Iei-integration NOVA-PV-D4251_D5251 v1.01 Instrukcja Użytkownika Pobierz pdf (Strona 170)

NOVA-PV-D5251/D4251 5.25" SBC

Page 156

computer is usually a male DE-9 connector.

DAC The Digital-to-Analog Converter (DAC) converts digital signals to

analog signals.

DDR Double Data Rate refers to a data bus transferring data on both the

rising and falling edges of the clock signal.

DMA Direct Memory Access (DMA) enables some peripheral devices to

bypass the system processor and communicate directly with the

system memory.

DIMM Dual Inline Memory Modules are a type of RAM that offer a 64-bit data

bus and have separate electrical contacts on each side of the module.

EHCI The Enhanced Host Controller Interface (EHCI) specification is a

GbE Gigabit Ethernet (GbE) is an Ethernet version that transfers data at 1.0

Gbps and complies with the

3IEEE 802.3-2005 standard.

GPIO General purpose input

IrDA Infrared Data Association (IrDA) specify infrared data transmission

protocols used to enable electronic devices to wirelessly communicate

with each other.

L1 Cache The Level 1 Cache (L1 Cache) is a small memory cache built into the

system processor.

L2 Cache The Level 2 Cache (L2 Cache) is an external processor memory cache.

LVDS Low-voltage differential signaling (LVDS) is a dual-wire, high-speed

differential electrical signaling system commonly used to connect LCD

displays to a computer.

MAC The Media Access Control (MAC) protocol enables several terminals or

network nodes to communicate in a LAN, or other multipoint networks.

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Iei-integration NOVA-PV-D4251_D5251 v1.01 Instrukcja Użytkownika Strona 170