Iei-integration WAFER-945GSE2 v1.03 Instrukcja Użytkownika Pobierz pdf (Strona 36)

WAFER-945GSE2 User Manual

Page 19

 ISA Interface

 SM Bus

 One analog line-level mono output: MONO_OUT

 Power-on Serial Bus Configuration

 Serial IRQ

 Optional FLASH ROM Interface

 Versatile power-on strapping options

 Supports NOGO function

 Single 33 MHz Clock Input

 +3.3V PCI I/F with +5V tolerant I/O buffers

 +5V ISA I/F and core Power Supply

2.5.6 Intel

ICH7-M PCIe Bus

The Intel® ICH7-M Southbridge chipset has four PCIe lanes. Two of the four PCIe lanes

are interfaced to PCIe GbE controller.

2.5.6.1 PCIe GbE Ethernet

Two PCIe lanes are connected to two Realtek RTL8111CP PCIe GbE controllers shown in

Figure 2-12 below.

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Iei-integration WAFER-945GSE2 v1.03 Instrukcja Użytkownika Strona 36