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2.5.3 Intel
®
ICH7-M Low Pin Count (LPC) Interface
The ICH7-M LPC interface complies with the LPC 1.1 specifications. The LPC bus from
the ICH7-M is connected to the following components:
BIOS chipset
Super I/O chipset
2.5.4 Intel
®
ICH7-M PCI Interface
The PCI interface on the ICH7-M is compliant with the PCI Revision 2.3 implementation.
Some of the features of the PCI interface are listed below.
PCI Revision 2.3 compliant
33MHz
5V tolerant PCI signals (except PME#)
Integrated PCI arbiter supports up to seven PCI bus masters
The PCI bus is connected to a PC/104-Plus connector as shown in
710HFigure 2-10.
Figure 2-10: PC/104-Plus Connector
- NOVA-945GSE 1
- Revision 2
- Packing List 6
- 553H193 12
- List of Figures 13
- List of Tables 16
- List of BIOS Menus 18
- 1 Introduction 19
- 1.1 Overview 20
- 1.2 NOVA-945GSE Overview 20
- Page 22 22
- Page 24 24
- 2 Detailed Specifications 26
- 2.1 Dimensions 27
- 2.2 Data Flow 28
- 702HFigure 29
- Figure 2-5 below 31
- Figure 2-5: Front Side Bus 31
- 704HFigure 2-6 below 32
- 706HFigure 2-7) 34
- Page 36 36
- 709HFigure 2-9 below 37
- 711HFigure 2-11 below 39
- Page 40 40
- 713HFigure 2-13 41
- 2.6 LPC Bus Components 43
- Page 44 44
- 3 Unpacking 48
- 3.1 Anti-static Precautions 49
- 3.2 Unpacking 49
- 3.3 Unpacking Checklist 50
- 3.3.2 Optional Items 51
- 4 Connectors 53
- 720H4.1.1 54
- Page 56 56
- 727HFigure 4-3 57
- 728HTable 4-3 57
- 1 +5V Standby 59
- 3 PS-ON 59
- 1 LINE_OUTR 2 LIR 60
- 3 GND 4 GND 60
- 5 LINE_OUTL 6 LIL 60
- 7 GND 8 GND 60
- 9 MIC_IN 10 N/A 60
- 1 LCD Backlight Control 61
- 2 GROUND 61
- 4 GROUND 61
- 5 BACKLIGHT Enable 61
- Page 62 62
- 4.3.6 CRT Connector 63
- 1 L_RED 2 DDC_CLK 64
- 3 L_GREEN 4 DDC_DATA 64
- 5 L_BLUE 6 GND 64
- 7 HSYNC 8 GND 64
- 9 VSYNC 10 GND 64
- 1 GND 2 VCC5 65
- 3 Output 3 4 Output 2 65
- 5 Output 1 6 Output 0 65
- 7 Input 3 8 Input 2 65
- 9 Input 1 10 Input 0 65
- 743HFigure 4-11 66
- 744HTable 4-11 66
- Page 68 68
- 787H747HFigure 4-13 69
- 788H748HTable 4-13 69
- 749HFigure 4-14 70
- 750HTable 4-14 70
- Page 72 72
- 755HFigure 4-17 74
- 756HTable 4-17 74
- 793H757HFigure 4-18 76
- 794H758HTable 4-18 76
- 1 DCD 2 DSR 78
- 3 RX 4 RTS 78
- 5 TX 6 CTS 78
- 7 DTR 8 RI 78
- 9 GND 10 N/C 78
- Page 80 80
- 1 GND 2 AGREEN_Y 81
- 3 GND 4 ARED_C 81
- 5 GND 6 ABLUE_CVBS 81
- Page 82 82
- 4.4.1 LAN Connectors 83
- 810H775HTable 4-26 84
- 5.1 Anti-static Precautions 86
- Read the user manual: 87
- Page 88 88
- 5.2.2 Installation Checklist 88
- 5.3 Unpacking 89
- 777HFigure 5-1) 90
- 778HFigure 5-1) 90
- 779HFigure 5-2. Step 0: 90
- Page 92 92
- CF Card Setup Description 93
- Open Slave Default 93
- Closed Master 93
- Load Optimal Defaults 94
- 832H791HTable 5-4 95
- 833H792HFigure 5-6 below 95
- 793HTable 5-5 95
- 794HFigure 5-7 95
- Short 2-3 +5V LVDS 98
- 5.6 Chassis Installation 99
- SATA power cable 100
- HDD cable 100
- LPT cable 100
- HDTV out cable 100
- NOVA-945GSE 5.25” SBC 101
- Page 101 101
- Page 102 102
- 810HFigure 5-13 104
- 813HFigure 5-15 106
- 6 AMI BIOS 108
- 6.1 Introduction 109
- Page 111 111
- 6.3 Advanced 112
- BIOS Menu 2: Advanced 113
- Page 115 115
- 877H829H6.3.2.1 appear 116
- Page 122 122
- DEFAULT 123
- Page 126 126
- CPU Fan PWM control 127
- Minimum Value: 0°C 127
- Maximum Value: 127°C 127
- Page 128 128
- Page 129 129
- 6.3.5 Power Configuration 129
- Page 130 130
- 6.3.6 APM Configuration 130
- Page 131 131
- EFAULT 132
- Page 133 133
- 6.3.7 Remote Configuration 133
- Page 134 134
- Page 135 135
- Page 136 136
- 6.3.8 USB Configuration 136
- 6.4 PCI/PnP 139
- 6.5 Boot 141
- BIOS Menu 14: Boot 142
- 6.6 Security 145
- 6.7 Chipset 146
- PCI/IGD DEFAULT 148
- Page 149 149
- 6.8 Exit 151
- Page 152 152
- 7 Software Drivers 153
- Page 154 154
- Page 155 155
- Page 156 156
- Page 157 157
- Page 158 158
- Page 159 159
- Page 160 160
- 7.4 VGA Driver Installation 161
- Page 162 162
- Page 163 163
- Page 164 164
- Page 165 165
- 7.5 LAN Driver Installation 166
- Page 167 167
- Page 168 168
- Page 169 169
- Page 170 170
- Page 171 171
- A BIOS Menu Options 172
- B Terminology 176
- Page 177 177
- Page 178 178
- Page 179 179
- Page 180 180
- C DIO Interface 181
- C.2 DIO Connector Pinouts 182
- D Watchdog Timer 184
- E Address Mapping 187
- E.1 I/O Address Map 188
- Page 189 189
- E.2 IRQ Address Map 190
- E.3 Memory Address Map 191
- F Hazardous Materials 192
- Disclosure 192
- Page 193 193
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